This invention relates generally to the field of matrix-array binary-logic read-only memory devices, more particularly to high-density programmable read-only memory (PROM) devices, and especially, to the portions of these devices used for reading the contents of the memory and presenting an output signal indicative of the information stored in memory.
PROMs have come into widespread use in a variety of computer and other logic-circuit applications since they offer the ability to retain data in a permanent, non-volatile form, such that no precautions need be taken to ensure the retention of data during power failures. They are thus used very successfully to retain the most basic and often-used programs and routines in a computer, for example.
The data stored in a PROM is retained by a large number of memory cells (4,000 to 64,000 and more in high-density types), each one of which holds a binary-logic 0 or 1 after data has been written into the PROM. Each memory cell is located at a discrete bit location within the matrix array of conductive rows and conductive columns, corresponding to the point of crossing of one row and one column. Accordingly, each cell has a unique address within the array corresponding to the identity of the row and column at whose juncture the cell is located.
Within each memory cell a binary 0 or 1 is represented simply by whether the cell does or does not provide a conductive path between the associated row and column. For this purpose, each cell may be series combination of a Schottky diode and a fusible link, connected to permit the flow of current from the column to the row across the bit location only if the fusible link is intact.
Throughout the remainder of this patent application, the presence of such a conductive path through an intact fusible link will be taken to represent a binary value of 0 stored in the associated cell. Conversely, if the link was blown during the process of writing data into the PROM, this will be taken to represent a binary 1 stored in the cell. Of course, the opposite logic convention could equally well be adopted in appropriate circumstances.
One method of reading the contents of a memory cell involves circuitry located on the PROM chip which applies a logic HIGH signal to one member of the associated row-column pair and a LOW to the other member of the pair. The presence of the fusible link can then be inferred from the voltage level at the addressed memory cell, which will be HIGH or LOW depending on whether the cell is conductive or not.
In PROMs of the sort with which this invention is concerned, the memory cells are individually read at very high speed by a technique which involves the selecting of the column and row of the cell and the application of a current source to the column while the associated row is held low, near ground. This scheme results in the voltage level of the column rising abruptly if the fuse is blown, representing a logic 1. The absence of this rise in voltage to a logic HIGH, indicating that the fuse is intact, represents a logic 0.
While this scheme works well, it has been carried out by circuit means which involve the provision of a separate current source for each of the columns. This has the disadvantage of producing unnecessary current consumption in the current sources associated with columns which are not selected for reading.
Such unnecessary current consumption has sometimes been tolerable in low-density PROMs, but as density has risen it has become an increasing problem. Moreover, the necessity to provide a separate current source for each column has resulted in limiting the current provided from each source in the interests of keeping power consumption and dissipation within acceptable limits.